1. Field of the Invention
The present invention relates to a semiconductor fabricating process and particularly relates to a semiconductor fabricating process using two layers of spacers to protect a stacked structure.
2. Description of Related Art
In a fabricating process of a semiconductor device of 0.13 um or smaller than 0.13 um, the steps for forming a gate structure are described as follows. First, a gate dielectric material layer, a gate material layer, a gate mask material layer, and a patterned photoresist layer are sequentially formed on a substrate. The gate mask material layer is, for example, formed by silicon oxynitride and serves as a dielectric anti-reflective coating layer (DARC layer). Then, the patterned photoresist layer is used as a mask to etch the gate mask material layer, so as to form a gate mask layer. Next, the gate mask layer is used as a mask to etch the gate material layer and the gate dielectric material layer, so as to form a gate and a gate dielectric layer. Thereafter, a deglazing process is performed and a hydrofluoric acid solution is used to remove impurities and a native oxide layer from the gate mask layer. Then, the gate mask layer is removed by a hot phosphoric acid solution to complete the fabrication of the gate structure.
However, the gate dielectric layer has low etching resistance to the hydrofluoric acid solution. As a consequence, the hydrofluoric acid solution may etch a portion of the gate dielectric layer during the deglazing process. In addition, the gate such as a doped polysilicon layer has low etching resistance to the hot phosphoric acid solution. Hence, the hot phosphoric acid solution may etch the gate and reduce the line width of the gate when the gate mask layer is removed. Consequently, the reliability and performance of the device are decreased.